The field of the present invention pertains to computer implemented integrated circuit simulators. More specifically, the field of the present invention pertains to circuit simulators that access an integrated circuit design that is represented by a hierarchical netlist.
Due to the great complexity of modern integrated circuit designs, they re represented by designers as xe2x80x9cnetists.xe2x80x9d Netlists contain descriptions of circuitry and the manner in which the circuitry is connected together. These netlists are stored in various computer readable medium in such a way that they can be processed by computer systems. Circuit simulators are computer implemented processes that can simulate the expected operation and behavior of a circuit design by applying a set of input signals to the netlist and propagating the resultant signals through the netlist to its output nodes. Circuit simulators can be used, in one way, to verify that a netlist properly performs its specified operation and/or to measure the performance of the design.
In the past, netlists were completely flattened in order to perform circuit simulation. Flattening is the process of taking a netlist that may be represented in multiple levels of a structured hierarchy and transforming it into a netlist that contains only leaf cells of a single level. Flattening is required because conventional circuit simulators perform subcircuit divisions based on channel connect boundaries. A netlist is divided into multiple subcircuits (e.g., xe2x80x9cpartitions) in order to reduce the complexity of the matrix computations that are required of the simulation processes. In other words, the netlist is broken down into smaller pieces to more readily perform the manageable matrix computations of each piece. The matrix computations result from multiple node voltage equations that need to be solved by the circuit simulator.
A xe2x80x9cchannel connectxe2x80x9d boundary attempts to divide a netlist into a subcircuit based on the drain-to-source connections of the transistors that make up the netlist. According to a channel connect boundary, drain-to-source connections have strong electrical coupling where drain-to-gate or source-to-gate connections have weak electrical coupling.
In more specific terms, in order to process an input event (e.g., for an event-driven simulator), the computer system needs to define a group of leaf cells that are touched by the event. Conventional simulators use a channel connect boundary partition process to determine this group of leaf cells and grouping is based on the source-to-drain connections of the circuit elements, e.g., for CMOS technology. Graph techniques are applied to define the partition and, according to these techniques, source-to-drain connections are followed until gates are reached. The circuit behavior of the partitions are then separately simulated, e.g., matrix computations are performed. Because the channel boundary partitions can be different for each event, the computer system requires that the entire netlist be completely flattened to leaf cells in order to property perform the circuit simulation.
However, the netlist representations of modern integrated circuit designs may contain multiple millions of leaf cells. Therefore, requiring that the entire netlist be flattened in order to perform simulation requires that the computer system contain a very large (and expensive) amount of computer memory resources in order to store and flatten the entire design. As a result, conventional circuit simulators operate on expensive and complex computer systems. It would be advantageous to provide a circuit simulator that produced accurate results but did not require the vast computer memory resources required of conventional circuit simulators.
Accordingly, the present invention provides a circuit simulator that produces accurate results but does not require the large computer memory resources required of conventional circuit simulators. The present invention further provides a circuit simulator, as above, that operates on an integrated circuit design that is represented by a hierarchical netlist and does not require flattening of the entire netlist in order to perform simulation. Further, the present invention provides a circuit simulator that advantageously utilizes the defined hierarchical boundaries of the netlist in order to produce the subcircuits that are used to simplify the matrix computations required of simulation. By using the defined hierarchical boundaries of the netlist in order to produce the subcircuits, many of the structural information of a cell can be shared among the simulation computations that utilize instances of the same cell, thereby reducing the amount of memory required to perform circuit simulation. These and other advantageous of the present invention not discussed above will become clear within discussions of the present invention presented herein.
A system and a method are described for performing circuit simulation on a integrated circuit design that is represented by a hierarchical netlist. The system and method utilize, in one embodiment, an event driven simulator that divides or xe2x80x9ccutsxe2x80x9d along the hierarchical boundaries of the input netlist in order to produce subcircuits that are then converted into Thevenin equivalent circuit models. Once a Thevenin equivalent circuit model is computed, matrix equations/computations are used to compute the cut node voltages and then sensitivity vectors may be used to determine the internal node voltages. The cut node voltages are stored in a flattened cut node voltage data structure that is dynamic. Internal node voltages may be stored in instance specific dynamic data structures. This is done for each event. In the event driven example, a group of leaf cells are identified that are touched by a given event. This group is then cut based on the hierarchical boundaries of the input netlist.
The system maintains the dynamic node voltages across the entire netlist and also maintains instance specific dynamic information for each cell. However, static information for a given cell is shared for each cell instance thereby reducing memory resources required to perform simulation for input hierarchical netlists that contain repeated cell instances. The present invention provides an accurate voltage and current simulation while requiring reduced memory resources for hierarchical netlists that contain repeated cell instances.
More specifically, an embodiment of the present invention includes a computer implemented method of simulating an integrated circuit design comprising the steps of: a) accessing an input netlist describing the integrated circuit design, the input netlist organized in a hierarchical fashion; b) in response to an event, determining a group of leaf cells of the netlist that are effected by the event; c) of the group of leaf cells, dividing the group into stages based on hierarchical boundaries as defined in the netlist; d) transforming each of the stages into a separate circuit model; e) using the circuit models to compute cut node voltages of the stages and recording, in computer memory, the cut node voltages; f) repeating the steps b)-e) for multiple events.
Embodiments include the above and wherein the circuit models are Thevenin equivalent circuit models. An embodiment of the present invention also includes a computer system operable according to the simulation method described above.